S912XHZ512F1VAG Datasheet, PDF (671/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 19
Enhanced Capture Timer (ECT16B8CV3)
Table 19-1. Revision History
Revision
Number
Revision Date
Sections
Affected
Description of Changes
V03.06
05 Aug 2009
19.3.2.15/19-69 update register PACTL bit4 PEDGE PT7 to IC7
3
update register PAFLG bit0 PAIF PT7 to IC7,update bit1 PAOVF PT3 to IC3
19.3.2.16/19-69 update register ICSYS bit3 TFMOD PTx to ICx
5
update register PBFLG bit1 PBOVF PT1 to IC1
19.3.2.24/19-70 update IC Queue Mode description.
1
19.3.2.29/19-70
6
19.4.1.1.2/19-71
7
V03.07
26 Aug 2009
19.3.2.2/19-680 - Add description, ?a counter overflow when TTOV[7] is set?, to be the
19.3.2.3/19-680 condition of channel 7 override event.
19.3.2.4/19-681 - Phrase the description of OC7M to make it more explicit
V03.08
04 May 2010 19.3.2.8/19-684 - Add Table 19-11
19.3.2.11/19-68 - TCRE descripgion part,add Note and Figure 19-17
7
19.1 Introduction
The HCS12 enhanced capture timer module has the features of the HCS12 standard timer module
enhanced by additional features in order to enlarge the field of applications, in particular for automotive
ABS applications.
This design specification describes the standard timer as well as the additional features.
The basic timer consists of a 16-bit, software-programmable counter driven by a prescaler. This timer can
be used for many purposes, including input waveform measurements while simultaneously generating an
output waveform. Pulse widths can vary from microseconds to many seconds.
A full access for the counter registers or the input capture/output compare registers will take place in one
clock cycle. Accessing high byte and low byte separately for all of these registers will not yield the same
result as accessing them in one word.
19.1.1 Features
• 16-bit buffer register for four input capture (IC) channels.
MC9S12XHZ512 Data Sheet, Rev. 1.06
Freescale Semiconductor
671