S912XHZ512F1VAG Datasheet, PDF (117/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3.13 Port V
Port V is associated with the stepper stall detect (SSD3 and SSD2) and motor controller (MC3 and MC2)
modules. Each pin is assigned to these modules according to the following priority: SSD3/SSD2 >
MC3/MC2 > general-purpose I/O.
If SSD3 module is enabled, the PV[7:4] pins are controlled by the SSD3 module. If SSD3 module is
disabled, the PV[7:4] pins are controlled by the motor control PWM channels 7 and 6 (MC3).
If SSD2 module is enabled, the PV[3:0] pins are controlled by the SSD2 module. If SSD2 module is
disabled, the PV[3:0] pins are controlled by the motor control PWM channels 5 and 4 (MC2).
Refer to the SSD and MC block description chapters for information on enabling and disabling the SSD
module and the motor control PWM channels respectively.
During reset, port V pins are configured as high-impedance inputs.
2.3.13.1 Port V I/O Register (PTV)
Module Base + 0x0040
R
W
MC:
SSD3/
SSD2
Reset
7
PTV7
M3C1P
M3SINP
0
6
PTV6
5
PTV5
4
PTV4
3
PTV3
2
PTV2
1
PTV1
0
PTV0
M3C1M
M3SINM
0
M3C0P
M3C0M
M2C1P
M2C1M
M3COSP M3COSM M2SINP
M2SINM
0
0
0
0
Figure 2-72. Port V I/O Register (PTV)
M2C0P
M2COSP
0
M2C0M
M2COSM
0
Read: Anytime. Write: anytime.
If the associated data direction bit (DDRVx) is set to 1 (output), a read returns the value of the I/O register
bit.
If the associated data direction bit (DDRVx) is set to 0 (input) and the slew rate is enabled, the associated
I/O register bit (PTVx) reads “1”.
If the associated data direction bit (DDRVx) is set to 0 (input) and the slew rate is disabled, a read returns
the value of the pin.
MC9S12XHZ512 Data Sheet, Rev. 1.06
Freescale Semiconductor
117