S912XHZ512F1VAG Datasheet, PDF (323/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 6
Security (S12X9SECV2)
Revision
Number
02.00
02.01
02.02
Revision
Date
27 Aug 2004
21 Feb 2007
19 Apr 2007
Table 6-1. Revision History
Sections
Affected
Description of Changes
reviewed and updated for S12XD architecture
added S12XE, S12XF and S12XS architectures
corrected statement about Backdoor key access via BDM on XE, XF, XS
6.1 Introduction
This specification describes the function of the security mechanism in the S12XD chip family (9SEC).
NOTE
No security feature is absolutely secure. However, Freescale’s strategy is to
make reading or copying the FLASH and/or EEPROM difficult for
unauthorized users.
6.1.1 Features
The user must be reminded that part of the security must lie with the application code. An extreme example
would be application code that dumps the contents of the internal memory. This would defeat the purpose
of security. At the same time, the user may also wish to put a backdoor in the application program. An
example of this is the user downloads a security key through the SCI, which allows access to a
programming routine that updates parameters stored in another section of the Flash memory.
The security features of the S12X chip family (in secure mode) are:
• Protect the content of non-volatile memories (Flash, EEPROM)
• Execution of NVM commands is restricted
• Disable access to internal memory via background debug module (BDM)
• Disable access to internal Flash/EEPROM in expanded modes
• Disable debugging features for the CPU and XGATE
6.1.2 Modes of Operation
Table 6-2 gives an overview over availability of security relevant features in unsecure and secure modes.
MC9S12XHZ512 Data Sheet, Rev. 1.06
Freescale Semiconductor
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