S912XHZ512F1VAG Datasheet, PDF (482/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 13 Inter-Integrated Circuit (IICV3) Block Description
13.2 External Signal Description
The IICV3 module has two external pins.
13.2.1 IIC_SCL — Serial Clock Line Pin
This is the bidirectional serial clock line (SCL) of the module, compatible to the IIC bus specification.
13.2.2 IIC_SDA — Serial Data Line Pin
This is the bidirectional serial data line (SDA) of the module, compatible to the IIC bus specification.
13.3 Memory Map and Register Definition
This section provides a detailed description of all memory and registers for the IIC module.
13.3.1 Register Descriptions
This section consists of register descriptions in address order. Each description includes a standard register
diagram with an associated figure number. Details of register bit and field function follow the register
diagrams, in bit order.
Register
Name
0x0000
IBAD
Bit 7
R
ADR7
W
6
ADR6
5
ADR5
4
ADR4
3
ADR3
2
ADR2
1
ADR1
Bit 0
0
0x0001
IBFD
R
IBC7
W
IBC6
IBC5
IBC4
IBC3
IBC2
IBC1
IBC0
0x0002
IBCR
R
IBEN
W
0
IBIE
MS/SL
Tx/Rx
TXAK
RSTA
0
IBSWAI
0x0003
R TCF
IAAS
IBB
0
SRW
RXAK
IBSR
W
IBAL
IBIF
0x0004
R
IBDR
D7
W
D6
D5
D4
D3
D2
D1
D0
0x0005
R
0
0
0
IBCR2
GCEN ADTYPE
W
ADR10 ADR9
ADR8
= Unimplemented or Reserved
Figure 13-2. IIC Register Summary
MC9S12XHZ512 Data Sheet, Rev. 1.06
482
Freescale Semiconductor