S912XHZ512F1VAG Datasheet, PDF (863/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Global Address [22:0]
Chapter 25 Memory Mapping Control (S12XMMCV3)
0 0 0 ^{Bit19 Bit18}
Bit12 Bit11
Bit0
RPAGE Register [7:0]
Address [11:0]
Field
7–0
RP[7:0]
Address: CPU Local Address
or BDM Local Address
Figure 25-12. RPAGE Address Mapping
NOTE
Because RAM page 0 has the same global address as the register space, it is
possible to write to registers through the RAM space when RPAGE = 0x00.
Table 25-12. RPAGE Field Descriptions
Description
RAM Page Index Bits 7–0 — These page index bits are used to select which of the 256 RAM array pages is to
be accessed in the RAM Page Window.
The reset value of 0xFD ensures that there is a linear RAM space available between addresses 0x1000 and
0x3FFF out of reset.
The fixed 4K page from 0x2000–0x2FFF of RAM is equivalent to page 254 (page number 0xFE).
The fixed 4K page from 0x3000–0x3FFF of RAM is equivalent to page 255 (page number 0xFF).
MC9S12XHZ512 Data Sheet, Rev. 1.06
Freescale Semiconductor
863