S912XHZ512F1VAG Datasheet, PDF (834/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 24 Interrupt (S12XINTV1)
24.1.4 Block Diagram
Figure 24-1 shows a block diagram of the XINT module.
Peripheral
Interrupt Requests
Non I Bit Maskable
Channels
IRQ Channel
Wake Up
CPU
Vector
Address
RQST
One Set Per Channel
(Up to 112 Channels)
XGATE
Requests
PRIOLVL2
PRIOLVL1
PRIOLVL0
Interrupt
Requests
INT_XGPRIO
IVBR
New
IPL
Current
IPL
Priority
Decoder
Wake up
XGATE
Vector
ID
XGATE
Interrupts
To XGATE Module
RQST
DMA Request Route,
PRIOLVLn Priority Level
= bits from the channel configuration
in the associated configuration register
INT_XGPRIO = XGATE Interrupt Priority
IVBR
= Interrupt Vector Base
IPL
= Interrupt Processing Level
Figure 24-1. XINT Block Diagram
MC9S12XHZ512 Data Sheet, Rev. 1.06
834
Freescale Semiconductor