S912XHZ512F1VAG Datasheet, PDF (530/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3)
14.3.2.17 MSCAN Identifier Acceptance Registers (CANIDAR0-7)
On reception, each message is written into the background receive buffer. The CPU is only signalled to
read the message if it passes the criteria in the identifier acceptance and identifier mask registers
(accepted); otherwise, the message is overwritten by the next message (dropped).
The acceptance registers of the MSCAN are applied on the IDR0–IDR3 registers (see Section 14.3.3.1,
“Identifier Registers (IDR0–IDR3)”) of incoming messages in a bit by bit manner (see Section 14.4.3,
“Identifier Acceptance Filter”).
For extended identifiers, all four acceptance and mask registers are applied. For standard identifiers, only
the first two (CANIDAR0/1, CANIDMR0/1) are applied.
Module Base + 0x0010 to Module Base + 0x0013
7
R
AC7
W
6
AC6
5
AC5
Reset
0
0
0
4
AC4
0
3
AC3
0
Access: User read/write⁽¹⁾
2
1
0
AC2
AC1
AC0
0
0
0
Figure 14-20. MSCAN Identifier Acceptance Registers (First Bank) — CANIDAR0–CANIDAR3
1. Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
Table 14-22. CANIDAR0–CANIDAR3 Register Field Descriptions
Field
Description
7-0
AC[7:0]
Acceptance Code Bits — AC[7:0] comprise a user-defined sequence of bits with which the corresponding bits
of the related identifier register (IDRn) of the receive message buffer are compared. The result of this comparison
is then masked with the corresponding identifier mask register.
Module Base + 0x0018 to Module Base + 0x001B
7
R
AC7
W
6
AC6
5
AC5
Reset
0
0
0
4
AC4
0
3
AC3
0
2
AC2
0
Access: User read/write⁽¹⁾
1
0
AC1
AC0
0
0
Figure 14-21. MSCAN Identifier Acceptance Registers (Second Bank) — CANIDAR4–CANIDAR7
1. Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
MC9S12XHZ512 Data Sheet, Rev. 1.06
530
Freescale Semiconductor