S912XHZ512F1VAG Datasheet, PDF (114/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3.12.2 Port U Input Register (PTIU)
Module Base + 0x0039
R
W
Reset
7
PTIU7
u
6
PTIU6
5
PTIU5
4
PTIU4
3
PTIU3
2
PTIU2
u
u
u
u
u
= Reserved or Unimplemented
u = Unaffected by reset
Figure 2-67. Port U Input Register (PTIU)
1
PTIU1
u
0
PTIU0
u
Read: Anytime. Write: Never, writes to this register have no effect.
If the associated slew rate control is enabled (digital input buffer is disabled), a read returns a “1”. If the
associated slew rate control is disabled (digital input buffer is enabled), a read returns the status of the
associated pin.
2.3.12.3 Port U Data Direction Register (DDRU)
Module Base + 0x003A
R
W
Reset
7
DDRU7
0
6
DDRU6
5
DDRU5
4
DDRU4
3
DDRU3
2
DDRU2
0
0
0
0
0
Figure 2-68. Port U Data Direction Register (DDRU)
1
DDRU1
0
0
DDRU0
0
Read: Anytime. Write: Anytime.
This register configures port pins PU[7:0] as either input or output.
When enabled, the SSD or MC modules force the I/O state to be an output for each associated pin and the
associated Data Direction Register bit has no effect. If the SSD and MC modules are disabled, the
corresponding Data Direction Register bits revert to control the I/O direction of the associated pins.
Table 2-53. DDRU Field Descriptions
Field
7:0
Data Direction Port U
DDRU[7:0] 0 Associated pin is configured as input.
1 Associated pin is configured as output.
Description
MC9S12XHZ512 Data Sheet, Rev. 1.06
114
Freescale Semiconductor