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S912XHZ512F1VAG Datasheet, PDF (331/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256 | |||
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Chapter 7
Clocks and Reset Generator (S12CRGV6)
7.1 Introduction
This speciï¬cation describes the function of the clocks and reset generator (CRG).
7.1.1 Features
The main features of this block are:
⢠Phase locked loop (PLL) frequency multiplier
â Reference divider
â Automatic bandwidth control mode for low-jitter operation
â Automatic frequency lock detector
â Interrupt request on entry or exit from locked condition
â Self clock mode in absence of reference clock
⢠System clock generator
â Clock quality check
â User selectable fast wake-up from Stop in self-clock mode for power saving and immediate
program execution
â Clock switch for either oscillator or PLL based system clocks
⢠Computer operating properly (COP) watchdog timer with time-out clear window
⢠System reset generation from the following possible sources:
â Power on reset
â Low voltage reset
â Illegal address reset
â COP reset
â Loss of clock reset
â External pin reset
⢠Real-time interrupt (RTI)
MC9S12XHZ512 Data Sheet, Rev. 1.06
Freescale Semiconductor
331
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