S912XHZ512F1VAG Datasheet, PDF (81/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

2.3.5.5 Slew Rate Control Register (SRCR)
Chapter 2 Port Integration Module (S12XHZPIMV1)
Module Base + 0x0055
7
6
R
0
SRRK
W
5
4
3
2
1
0
0
SRRE
SRRD
SRRC
SRRB
SRRA
Reset
0
0
0
0
0
0
0
0
= Reserved or Unimplemented
Figure 2-18. Slew Rate Control Register (SRCR)
Read: Anytime. Write: Anytime.
This register enables the slew rate control and disables the digital input buffer for the pins associated with
ports A, B, C, D, E, and K.
Table 2-14. SRCR Field Descriptions
Field
7
SRRK
4
SRRE
3
SRRD
2
SRRC
1
SRRB
0
SRRA
Description
Slew Rate of Port K
0 Disables slew rate control and enables digital input buffer for all port K pins.
1 Enables slew rate control and disables digital input buffer for all port K pins.
Slew Rate of Port E
0 Disables slew rate control and enables digital input buffer for all port E pins.
1 Enables slew rate control and disables digital input buffer for all port E pins.
Slew Rate of Port D
0 Disables slew rate control and enables digital input buffer for all port D pins.
1 Enables slew rate control and disables digital input buffer for all port D pins.
Slew Rate of Port C
0 Disables slew rate control and enables digital input buffer for all port C pins.
1 Enables slew rate control and disables digital input buffer for all port C pins.
Slew Rate of Port B
0 Disables slew rate control and enables digital input buffer for all port B pins.
1 Enables slew rate control and disables digital input buffer for all port B pins.
Slew Rate of Port A
0 Disables slew rate control and enables digital input buffer for all port A pins.
1 Enables slew rate control and disables digital input buffer for all port A pins.
MC9S12XHZ512 Data Sheet, Rev. 1.06
Freescale Semiconductor
81