S912XHZ512F1VAG Datasheet, PDF (47/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 1 MC9S12XHZ Family Device Overview
1.3 System Clock Description
The clock and reset generator module (CRG) provides the internal clock signals for the core and all
peripheral modules. Figure 1-10 shows the clock connections from the CRG to all modules.
Consult the CRG block description chapter for details on clock generation.
SSD0 . . SSD5
CAN0 & CAN1 IIC0 & IIC1 SCI0 & SCI1
MC
LCD
SPI
Bus Clock
EXTAL
XTAL
CRG
Oscillator Clock
Core Clock
PIT
ECT
PIM
RAM
S12X
XGATE
FLASH
EEPROM
Figure 1-10. Clock Connections
The MCU’s system clock can be supplied in several ways enabling a range of system operating frequencies
to be supported:
• The on-chip phase locked loop (PLL)
• the PLL self clocking
• the oscillator
The clock generated by the PLL or oscillator provides the main system clock frequencies core clock and
bus clock. As shown in Figure 1-10, this system clocks are used throughout the MCU to drive the core, the
memories, and the peripherals.
MC9S12XHZ512 Data Sheet, Rev. 1.06
Freescale Semiconductor
47