S912XHZ512F1VAG Datasheet, PDF (95/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

2.3.8.8 Port M Slew Rate Register (SRRM)
Chapter 2 Port Integration Module (S12XHZPIMV1)
Module Base + 0x003B
7
R
0
W
6
5
4
3
2
1
0
0
0
SRRM5
SRRM4
SRRM3
SRRM2
SRRM1
Reset
0
0
0
0
0
0
0
0
= Reserved or Unimplemented
Figure 2-41. Port M Slew Rate Register (SRRM)
Read: Anytime. Write: Anytime.
This register enables the slew rate control and disables the digital input buffer for port pins PM[5:1].
Table 2-31. SRRM Field Descriptions
Field
Description
5:1
Slew Rate Port M
SRRM[5:1] 0 Disables slew rate control and enables digital input buffer.
1 Enables slew rate control and disables digital input buffer.
MC9S12XHZ512 Data Sheet, Rev. 1.06
Freescale Semiconductor
95