S912XHZ512F1VAG Datasheet, PDF (79/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

2.3.5.3 ECLK Control Register (ECLKCR)
Chapter 2 Port Integration Module (S12XHZPIMV1)
Module Base + 0x0055
7
6
5
4
3
2
R
0
0
0
0
NECLK
NCLKX2
W
Reset
0¹
1
0
0
0
0
= Reserved or Unimplemented
Figure 2-16. ECLK Control Register (ECLKCR)
1 _{NECLK reset value is 1 in emulation single-chip and normal single-chip modes.}
1
EDIV1
0
0
EDIV0
0
Read: Anytime. Write: Anytime.
The ECLKCTL register is used to control the availability of the free-running clocks and the free-running
clock divider.
Table 2-11. ECLKCTL Field Descriptions
Field
Description
7
NECLK
6
NCLKX2
1–0
EDIV[1:0]
No ECLK — This bit controls the availability of a free-running clock on the ECLK pin. Clock output is always
active in emulation modes and if enabled in all other operating modes.
0 ECLK enabled
1 ECLK disabled
No ECLKX2 — This bit controls the availability of a free-running clock on the ECLKX2 pin. This clock has a fixed
rate of twice the internal bus clock. Clock output is always active in emulation modes and if enabled in all other
operating modes.
0 ECLKX2 is enabled
1 ECLKX2 is disabled
Free-Running ECLK Divider — These bits determine the rate of the free-running clock on the ECLK pinr. The
usage of the bits is shown in Table 2-12. Divider is always disabled in emulation modes and active as
programmed in all other operating modes.
Table 2-12. Free-Running ECLK Clock Rate
EDIV[1:0]
00
01
10
11
Rate of Free-Running ECLK
ECLK = Bus clock rate
ECLK = Bus clock rate divided by 2
ECLK = Bus clock rate divided by 3
ECLK = Bus clock rate divided by 4
MC9S12XHZ512 Data Sheet, Rev. 1.06
Freescale Semiconductor
79