S912XHZ512F1VAG Datasheet, PDF (76/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 2 Port Integration Module (S12XHZPIMV1)
This register configures port pins PK[7:0] as either input or output.If a LCD frontplane driver is enabled
(and LCD module is enabled), it outputs an analog signal to the corresponding pin and the associated Data
Direction Register bit has no effect. If a LCD frontplane driver is disabled (or LCD module is disabled),
the corresponding Data Direction Register bit reverts to control the I/O direction of the associated pin.
Table 2-8. DDRK Field Descriptions
Field
7:0
Data Direction Port K
DDRK[7:0] 0 Associated pin is configured as input.
1 Associated pin is configured as output.
Description
MC9S12XHZ512 Data Sheet, Rev. 1.06
76
Freescale Semiconductor