S912XHZ512F1VAG Datasheet, PDF (812/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 23 External Bus Interface (S12XEBIV3)
23.3 Memory Map and Register Definition
This section provides a detailed description of all registers accessible in the XEBI.
23.3.1 Module Memory Map
The registers associated with the XEBI block are shown in Figure 23-2.
Register
Name
Bit 7
6
5
4
3
2
1
Bit 0
0x0E
R
0
EBICTL0
ITHRS
W
HDBE
ASIZ4
ASIZ3
ASIZ2
ASIZ1
ASIZ0
0x0F
EBICTL1
R
0
0
0
0
EWAITE
EXSTR2
W
= Unimplemented or Reserved
Figure 23-2. XEBI Register Summary
EXSTR1
EXSTR0
23.3.2 Register Descriptions
The following sub-sections provide a detailed description of each register and the individual register bits.
All control bits can be written anytime, but this may have no effect on the related function in certain
operating modes. This allows specific configurations to be set up before changing into the target operating
mode.
NOTE
Depending on the operating mode an available function may be enabled,
disabled or depend on the control register bit. Reading the register bits will
reflect the status of related function only if the current operating mode
allows user control. Please refer the individual bit descriptions.
MC9S12XHZ512 Data Sheet, Rev. 1.06
812
Freescale Semiconductor