S912XHZ512F1VAG Datasheet, PDF (571/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 15 Serial Communication Interface (S12SCIV5)
15.3.2.5 SCI Alternative Control Register 2 (SCIACR2)
Module Base + 0x0002
7
6
5
4
R
0
0
0
0
W
Reset
0
0
0
0
= Unimplemented or Reserved
3
2
1
0
BERRM1 BERRM0
0
0
0
Figure 15-8. SCI Alternative Control Register 2 (SCIACR2)
Read: Anytime, if AMAP = 1
Write: Anytime, if AMAP = 1
0
BKDFE
0
Table 15-8. SCIACR2 Field Descriptions
Field
Description
2:1
Bit Error Mode — Those two bits determines the functionality of the bit error detect feature. See Table 15-9.
BERRM[1:0]
0
BKDFE
Break Detect Feature Enable — BKDFE enables the break detect circuitry.
0 Break detect circuit disabled
1 Break detect circuit enabled
BERRM1
0
0
1
1
Table 15-9. Bit Error Mode Coding
BERRM0
Function
0
Bit error detect circuit is disabled
1
Receive input sampling occurs during the 9th time tick of a transmitted bit
(refer to Figure 15-19)
0
Receive input sampling occurs during the 13th time tick of a transmitted bit
(refer to Figure 15-19)
1
Reserved
MC9S12XHZ512 Data Sheet, Rev. 1.06
Freescale Semiconductor
571