S912XHZ512F1VAG Datasheet, PDF (632/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 17 Periodic Interrupt Timer (S12PIT24B4CV1)
17.3.0.6 PIT Time-Out Flag Register (PITTF)
Module Base + 0x0005
7
6
5
4
R
0
0
0
0
W
Reset
0
0
0
0
= Unimplemented or Reserved
3
PTF3
0
2
PTF2
0
Figure 17-8. PIT Time-Out Flag Register (PITTF)
Read: Anytime
Write: Anytime (write to clear); writes to the reserved bits have no effect
Table 17-6. PITTF Field Descriptions
1
PTF1
0
0
PTF0
0
Field
3:0
PTF[3:0]
Description
PIT Time-out Flag Bits for Timer Channel 3:0 — PTF is set when the corresponding 16-bit timer modulus
down-counter and the selected 8-bit micro timer modulus down-counter have counted to zero. The flag can be
cleared by writing a one to the flag bit. Writing a zero has no effect. If flag clearing by writing a one and flag setting
happen in the same bus clock cycle, the flag remains set. The flag bits are cleared if the PIT module is disabled
or if the corresponding timer channel is disabled.
0 Time-out of the corresponding PIT channel has not yet occurred.
1 Time-out of the corresponding PIT channel has occurred.
17.3.0.7 PIT Micro Timer Load Register 0 to 1 (PITMTLD0–1)
Module Base + 0x0006
R
W
Reset
7
PMTLD7
0
6
PMTLD6
5
PMTLD5
4
PMTLD4
3
PMTLD3
2
PMTLD2
1
PMTLD1
0
0
0
0
0
0
Figure 17-9. PIT Micro Timer Load Register 0 (PITMTLD0)
Module Base + 0x0007
R
W
Reset
7
PMTLD7
0
Read: Anytime
Write: Anytime
6
PMTLD6
5
PMTLD5
4
PMTLD4
3
PMTLD3
2
PMTLD2
1
PMTLD1
0
0
0
0
0
0
Figure 17-10. PIT Micro Timer Load Register 1 (PITMTLD1)
0
PMTLD0
0
0
PMTLD0
0
MC9S12XHZ512 Data Sheet, Rev. 1.06
632
Freescale Semiconductor