S912XHZ512F1VAG Datasheet, PDF (224/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 5 XGATE (S12XGATEV2)
5.3.1.7 XGATE Condition Code Register (XGCCR)
The XGCCR register (Figure 5-9) provides access to the RISC core’s condition code register.
Module Base +0x001D
7
6
5
4
R
0
0
0
0
W
Reset
0
0
0
0
= Unimplemented or Reserved
3
XGN
0
2
XGZ
0
Figure 5-9. XGATE Condition Code Register (XGCCR)
1
XGV
0
0
XGC
0
Read: In debug mode if unsecured
Write: In debug mode if unsecured
Table 5-7. XGCCR Field Descriptions
Field
3
XGN
2
XGZ
1
XGV
0
XGC
Sign Flag — The RISC core’s Sign flag
Description
Zero Flag — The RISC core’s Zero flag
Overflow Flag — The RISC core’s Overflow flag
Carry Flag — The RISC core’s Carry flag
MC9S12XHZ512 Data Sheet, Rev. 1.06
224
Freescale Semiconductor