S912XHZ512F1VAG Datasheet, PDF (798/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 22 S12X Debug (S12XDBGV3) Module
22.4.5.3.1 Information Byte Organization
The format of the control information byte is dependent upon the active trace mode as described below. In
Normal, Loop1, or Pure PC modes tracing of XGATE activity, XINF is used to store control information.
In Normal, Loop1, or Pure PC modes tracing of CPU12X activity, CINF is used to store control
information. In Detail Mode, CXINF contains the control information
XGATE Information Byte
Bit 7
XSD
Bit 6
XSOT
Bit 5
XCOT
Bit 4
XDV
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Figure 22-23. XGATE Information Byte XINF
Table 22-44. XINF Field Descriptions
Field
7
XSD
6
XSOT
5
XCOT
4
XDV
Description
Source Destination Indicator — This bit indicates if the corresponding stored address is a source or destination
address. This is only used in Normal and Loop1 mode tracing.
0 Source address
1 Destination address or Start of Thread or Continuation of Thread
Start Of Thread Indicator — This bit indicates that the corresponding stored address is a start of thread
address. This is only used in Normal and Loop1 mode tracing.
NOTE. This bit only has effect on devices where the XGATE module supports multiple interrupt levels.
0 Stored address not from a start of thread
1 Stored address from a start of thread
Continuation Of Thread Indicator — This bit indicates that the corresponding stored address is the first
address following a return from a higher priority thread. This is only used in Normal and Loop1 mode tracing.
NOTE. This bit only has effect on devices where the XGATE module supports multiple interrupt levels.
0 Stored address not from a continuation of thread
1 Stored address from a continuation of thread
Data Invalid Indicator — This bit indicates if the trace buffer entry is invalid. It is only used when tracing from
both sources in Normal, Loop1 and Pure PC modes, to indicate that the XGATE trace buffer entry is valid.
0 Trace buffer entry is invalid
1 Trace buffer entry is valid
XGATE info bit setting
XGATE FLOW
SOT1
SOT2 JAL
RTS COT1
RTS
XSD
XSOT
XCOT
Figure 22-24. XGATE info bit setting
Figure 22-24 indicates the XGATE information bit setting when switching between threads, the initial
thread starting at SOT1 and continuing at COT1 after the higher priority thread2 has ended.
MC9S12XHZ512 Data Sheet, Rev. 1.06
798
Freescale Semiconductor