S912XHZ512F1VAG Datasheet, PDF (630/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 17 Periodic Interrupt Timer (S12PIT24B4CV1)
17.3.0.2 PIT Force Load Timer Register (PITFLT)
Module Base + 0x0001
7
6
5
4
R
0
0
0
0
W
Reset
0
0
0
0
= Unimplemented or Reserved
3
0
PFLT3
0
2
0
PFLT2
0
Figure 17-4. PIT Force Load Timer Register (PITFLT)
Read: Anytime
Write: Anytime; writes to the reserved bits have no effect
Table 17-2. PITFLT Field Descriptions
1
0
PFLT1
0
0
0
PFLT0
0
Field
Description
3:0
PFLT[3:0]
PIT Force Load Bits for Timer 3-0 — These bits have only an effect if the corresponding timer channel (PCE
set) is enabled and if the PIT module is enabled (PITE set). Writing a one into a PFLT bit loads the corresponding
16-bit timer load register into the 16-bit timer down-counter. Writing a zero has no effect. Reading these bits will
always return zero.
17.3.0.3 PIT Channel Enable Register (PITCE)
Module Base + 0x0002
7
6
5
4
R
0
0
0
0
W
Reset
0
0
0
0
= Unimplemented or Reserved
3
PCE3
0
2
PCE2
0
Figure 17-5. PIT Channel Enable Register (PITCE)
Read: Anytime
Write: Anytime; writes to the reserved bits have no effect
Table 17-3. PITCE Field Descriptions
1
PCE1
0
0
PCE0
0
Field
Description
3:0
PCE[3:0]
PIT Enable Bits for Timer Channel 3:0 — These bits enable the PIT channels 3-0. If PCE is cleared, the PIT
channel is disabled and the corresponding flag bit in the PITTF register is cleared. When PCE is set, and if the
PIT module is enabled (PITE = 1) the 16-bit timer counter is loaded with the start count value and starts
down-counting.
0 The corresponding PIT channel is disabled.
1 The corresponding PIT channel is enabled.
MC9S12XHZ512 Data Sheet, Rev. 1.06
630
Freescale Semiconductor