S912XHZ512F1VAG Datasheet, PDF (894/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Appendix A Electrical Characteristics
A.1.6 ESD Protection and Latch-up Immunity
All ESD testing is in conformity with CDF-AEC-Q100 stress test qualification for automotive grade
integrated circuits. During the device qualification ESD stresses were performed for the Human Body
Model (HBM) and the Charge Device Model.
A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
Table A-2. ESD and Latch-up Test Conditions
Model
Human Body
Latch-up
Description
Series resistance
Storage capacitance
Number of pulse per pin
Positive
Negative
Minimum input voltage limit
Maximum input voltage limit
Symbol
R1
C
—
—
Value
1500
100
3
3
–2.5
7.5
Unit
Ohm
pF
V
V
Num
1
2
3
4
Table A-3. ESD and Latch-Up Protection Characteristics
C
Rating
C Human Body Model (HBM)
C Charge Device Model (CDM)
C Latch-up current at T_A = 125°C
Positive
Negative
C Latch-up current at T_A = 27°C
Positive
Negative
Symbol
V_HBM
V_CDM
I_LAT
I_LAT
Min
2000
500
+100
–100
+200
–200
Max
Unit
—
V
—
V
mA
—
—
mA
—
—
MC9S12XHZ512 Data Sheet, Rev. 1.06
894
Freescale Semiconductor