S912XHZ512F1VAG Datasheet, PDF (644/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 18 Pulse-Width Modulator (S12PWM8B8CV1)
Register
Name
Bit 7
6
5
4
3
2
1
Bit 0
0x001A R
PWMPER6 _W
Bit 7
6
5
4
3
2
1
Bit 0
0x001B R
PWMPER7 _W
Bit 7
6
5
4
3
2
1
Bit 0
0x001C R
PWMDTY0 _W
Bit 7
6
5
4
3
2
1
Bit 0
0x001D R
PWMDTY1 _W
Bit 7
6
5
4
3
2
1
Bit 0
0x001E R
PWMDTY2 _W
Bit 7
6
5
4
3
2
1
Bit 0
0x001F R
PWMDTY3 _W
Bit 7
6
5
4
3
2
1
Bit 0
0x0010 R
PWMDTY4 _W
Bit 7
6
5
4
3
2
1
Bit 0
0x0021 R
PWMDTY5 _W
Bit 7
6
5
4
3
2
1
Bit 0
0x0022 R
PWMDTY6 _W
Bit 7
6
5
4
3
2
1
Bit 0
0x0023 R
PWMDTY7 _W
Bit 7
6
5
4
3
2
1
Bit 0
0x0024 R
0
0
PWM7IN
PWMSDN _W ^PWMIF
PWMIE
PWMLVL
PWMRSTRT
PWM7INL PWM7ENA
= Unimplemented or Reserved
Figure 18-2. PWM Register Summary (Sheet 3 of 3)
1 _{Intended for factory test purposes only.}
18.3.2.1 PWM Enable Register (PWME)
Each PWM channel has an enable bit (PWMEx) to start its waveform output. When any of the PWMEx
bits are set (PWMEx = 1), the associated PWM output is enabled immediately. However, the actual PWM
waveform is not available on the associated PWM output until its clock source begins its next cycle due to
the synchronization of PWMEx and the clock source.
NOTE
The first PWM cycle after enabling the channel can be irregular.
MC9S12XHZ512 Data Sheet, Rev. 1.06
644
Freescale Semiconductor