S912XHZ512F1VAG Datasheet, PDF (795/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 22 S12X Debug (S12XDBGV3) Module
• Destination address of RTI, RTS, and RTC instructions.
• Vector address of interrupts, except for SWI and BDM vectors
LBRA, BRA, BSR, BGND as well as non-indexed JMP, JSR, and CALL instructions are not classified as
change of flow and are not stored in the trace buffer.
COF addresses are defined as follows for the XGATE:
• Source address of taken conditional branches
• Destination address of indexed JAL instructions.
• First XGATE code address in a thread
Change-of-flow addresses stored include the full 23-bit address bus of CPU12X, the 16-bit address bus for
the XGATE module and an information byte, which contains a source/destination bit to indicate whether
the stored address was a source address or destination address.
NOTE
When an CPU12X COF instruction with destination address is executed, the
destination address is stored to the trace buffer on instruction completion,
indicating the COF has taken place. If an interrupt occurs simultaneously
then the next instruction carried out is actually from the interrupt service
routine. The instruction at the destination address of the original program
flow gets exectuted after the interrupt service routine.
In the following example an IRQ interrupt occurs during execution of the
indexed JMP at address MARK1. The BRN at the destination (SUB_1) is
not executed until after the IRQ service routine but the destination address
is entered into the trace buffer to indicate that the indexed JMP COF has
taken place.
LDX
MARK1 JMP
MARK2 NOP
#SUB_1
0,X
; IRQ interrupt occurs during execution of this
;
SUB_1
ADDR1
BRN
NOP
DBNE
*
A,PART5
; JMP Destination address TRACE BUFFER ENTRY 1
; RTI Destination address TRACE BUFFER ENTRY 3
;
; Source address TRACE BUFFER ENTRY 4
IRQ_ISR LDAB #$F0
; IRQ Vector $FFF2 = TRACE BUFFER ENTRY 2
STAB VAR_C1
RTI
;
The execution flow taking into account the IRQ is as follows
LDX
#SUB_1
MARK1 JMP
0,X
;
IRQ_ISR LDAB #$F0
;
STAB VAR_C1
RTI
;
SUB_1 BRN
*
NOP
;
ADDR1 DBNE A,PART5
;
MC9S12XHZ512 Data Sheet Rev. 1.06
Freescale Semiconductor
795