S912XHZ512F1VAG Datasheet, PDF (703/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
19.3.2.25 Output Compare Pin Disconnect Register (OCPD)
Module Base + 0x002C
R
W
Reset
7
OCPD7
0
6
OCPD6
0
5
OCPD5
0
4
OCPD4
0
3
OCPD3
0
2
OCPD2
0
1
OCPD1
0
Figure 19-48. Output Compare Pin Disconnect Register (OCPD)
Read: Anytime
Write: Anytime
All bits reset to zero.
0
OCPD0
0
Table 19-32. OCPD Field Descriptions
Field
Description
7:0
OCPD[7:0]
Output Compare Pin Disconnect Bits
0 Enables the timer channel IO port. Output Compare actions will occur on the channel pin. These bits do not
affect the input capture or pulse accumulator functions.
1 Disables the timer channel IO port. Output Compare actions will not affect on the channel pin; the output
compare flag will still be set on an Output Compare event.
19.3.2.26 Precision Timer Prescaler Select Register (PTPSR)
Module Base + 0x002E
R
W
Reset
7
PTPS7
0
6
PTPS6
5
PTPS5
4
PTPS4
3
PTPS3
2
PTPS2
1
PTPS1
0
0
0
0
0
0
Figure 19-49. Precision Timer Prescaler Select Register (PTPSR)
Read: Anytime
Write: Anytime
All bits reset to zero.
0
PTPS0
0
Table 19-33. PTPSR Field Descriptions
Field
Description
7:0
PTPS[7:0]
Precision Timer Prescaler Select Bits — These eight bits specify the division rate of the main Timer prescaler.
These are effective only when the PRNT bit of TSCR1 is set to 1. Table 19-34 shows some selection examples
in this case.
The newly selected prescale factor will not take effect until the next synchronized edge where all prescale counter
stages equal zero.
MC9S12XHZ512 Data Sheet Rev. 1.06
Freescale Semiconductor
703