S912XHZ512F1VAG Datasheet, PDF (74/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 2 Port Integration Module (S12XHZPIMV1)
If the associated data direction bit (DDREx) is set to 0 (input) and the LCD frontplane driver is enabled
(and LCD module is enabled), the associated I/O register bit (PTEx) reads “1”.
If the associated data direction bit (DDREx) is set to 0 (input) and the LCD frontplane driver is disabled
(or LCD module is disabled), a read returns the value of the pin.
2.3.3.2 Port E Data Direction Register (DDRE)
Module Base + 0x0055
7
6
5
4
3
2
1
0
R
0
0
DDRE7
W
DDRE6
DDRE5
DDRE4
DDRE3
DDRE2
Reset
0
0
0
0
0
0
0
0
= Reserved or Unimplemented
Figure 2-11. Port E Data Direction Register (DDRE)
Read: Anytime. Write: Anytime.
This register configures port pins PE[7:0] as either input or output.If a LCD frontplane driver is enabled
(and LCD module is enabled), it outputs an analog signal to the corresponding pin and the associated Data
Direction Register bit has no effect. If a LCD frontplane driver is disabled (or LCD module is disabled),
the corresponding Data Direction Register bit reverts to control the I/O direction of the associated pin.
Table 2-7. DDRE Field Descriptions
Field
7:2
Data Direction Port E
DDRE[7:2] 0 Associated pin is configured as input.
1 Associated pin is configured as output.
Description
MC9S12XHZ512 Data Sheet, Rev. 1.06
74
Freescale Semiconductor