S912XHZ512F1VAG Datasheet, PDF (305/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 5 XGATE (S12XGATEV2)
STB
Store Byte to Memory
(Low Byte)
STB
Operation
RS.L ⇒ M[RB, #OFFS5]
RS.L ⇒ M[RB, RI]
RS.L ⇒ M[RB, RI]; RI+1 ⇒ RI;
RI–1 ⇒ RI; RS.L ⇒ M[RB, RI]¹
Stores the low byte of register RD to memory.
CCR Effects
NZVC
————
N: Not affected.
Z: Not affected.
V: Not affected.
C: Not affected.
Code and CPU Cycles
Source Form
STB RS, (RB, #OFFS5),
STB RS, (RB, RI)
STB RS, (RB, RI+)
STB RS, (RB, -RI)
Address
Mode
IDO5
IDR
IDR+
-IDR
01010
01110
01110
01110
Machine Code
RS
RB
RS
RB
RS
RB
RS
RB
Cycles
OFFS5
Pw
RI 0 0 Pw
RI 0 1 Pw
RI 1 0 Pw
1. If the same general purpose register is used as index (RI) and source register (RS), the unmodified content of the source
register is written to the memory: RS.L ⇒ M[RB, RS-1]; RS-1 ⇒ RS
MC9S12XHZ512 Data Sheet, Rev. 1.06
Freescale Semiconductor
305