S912XHZ512F1VAG Datasheet, PDF (737/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 20 Voltage Regulator (S12VREG3V3V5)
The API Trimming bits APITR[5:0] must be set so the minimum period equals 0.2 ms if stable frequency
is desired.
See Table 20-6 for the trimming effect of APITR.
NOTE
The first period after enabling the counter by APIFE might be reduced.
The API internal RC oscillator clock is not available if VREG_3V3 is in
Shutdown Mode.
20.4.8 Resets
This section describes how VREG_3V3 controls the reset of the MCU.The reset values of registers and
signals are provided in Section 20.3, “Memory Map and Register Definition”. Possible reset sources are
listed in Table 20-9.
Table 20-9. Reset Sources
Reset Source
Power-on reset
Low-voltage reset
Local Enable
Always active
Available only in full peformance mode
20.4.9 Description of Reset Operation
20.4.9.1 Power-On Reset (POR)
During chip power-up the digital core may not work if its supply voltage V_DD is below the POR
deassertion level (V_PORD). Therefore, signal POR, which forces the other blocks of the device into reset,
is kept high until V_DD exceeds V_PORD. The MCU will run the start-up sequence after POR deassertion.
The power-on reset is active in all operation modes of VREG_3V3.
20.4.9.2 Low-Voltage Reset (LVR)
For details on low-voltage reset, see Section 20.4.5, “Low-Voltage Reset (LVR)”.
20.4.10 Interrupts
This section describes all interrupts originated by VREG_3V3.
The interrupt vectors requested by VREG_3V3 are listed in Table 20-10. Vector addresses and interrupt
priorities are defined at MCU level.
Table 20-10. Interrupt Vectors
Interrupt Source
Low-voltage interrupt (LVI)
Local Enable
LVIE = 1; available only in full peformance
mode
MC9S12XHZ512 Data Sheet, Rev. 1.06
Freescale Semiconductor
737