S912XHZ512F1VAG Datasheet, PDF (69/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

2.3.1.2 Port B I/O Register (PTB)
Chapter 2 Port Integration Module (S12XHZPIMV1)
Module Base + 0x0051
R
W
XEBI:
7
PTB7
ADDR7
mux
IVD7
LCD: FP7
Reset
0
6
PTB6
5
PTB5
4
PTB4
3
PTB3
2
PTB2
ADDR6
mux
IVD6
FP6
0
ADDR5
mux
IVD5
ADDR4
mux
IVD4
ADDR3
mux
IVD3
ADDR2
mux
IVD2
FP5
FP4
FP3
FP2
0
0
0
0
Figure 2-3. Port B I/O Register (PTB)
1
PTB1
ADDR1
mux
IVD1
FP1
0
0
PTB0
ADDR0
mux
IVD0
or UDS
FP0
0
Read: Anytime. Write: Anytime.
If the associated data direction bit (DDRBx) is set to 1 (output), a read returns the value of the I/O register
bit.
If the associated data direction bit (DDRBx) is set to 0 (input) and the LCD frontplane driver is enabled
(and LCD module is enabled), the associated I/O register bit (PTBx) reads “1”.
If the associated data direction bit (DDRBx) is set to 0 (input) and the LCD frontplane driver is disabled
(or LCD module is disabled), a read returns the value of the pin.
2.3.1.3 Port A Data Direction Register (DDRA)
Module Base + 0x0055
R
W
Reset
7
DDRA7
0
6
DDRA6
5
DDRA5
4
DDRA4
3
DDRA3
2
DDRA2
0
0
0
0
0
Figure 2-4. Port A Data Direction Register (DDRA)
1
DDRA1
0
0
DDRA0
0
Read: Anytime. Write: Anytime.
This register configures port pins PA[7:0] as either input or output.If a LCD frontplane driver is enabled
(and LCD module is enabled), it outputs an analog signal to the corresponding pin and the associated Data
Direction Register bit has no effect. If a LCD frontplane driver is disabled (or LCD module is disabled),
the corresponding Data Direction Register bit reverts to control the I/O direction of the associated pin.
MC9S12XHZ512 Data Sheet, Rev. 1.06
Freescale Semiconductor
69