S912XHZ512F1VAG Datasheet, PDF (416/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 10 Liquid Crystal Display (LCD32F4BV1) Block Description
10.3.2.2 LCD Control Register 1 (LCDCR1)
Module Base + 0x0001
7
6
5
4
3
2
R
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
Unimplemented or Reserved
Figure 10-3. LCD Control Register 1 (LCDCR1)
Read: anytime
Write: anytime
Table 10-4. LCDCR1 Field Descriptions
1
0
LCDSWAI LCDRPSTP
0
0
Field
Description
1
LCD Stop in Wait Mode — This bit controls the LCD operation while in wait mode.
LCDSWAI 0 LCD operates normally in wait mode.
1 Stop LCD32F4BV1 driver system when in wait mode.
0
LCD Run in Pseudo Stop Mode — This bit controls the LCD operation while in pseudo stop mode.
LCDRPSTP 0 Stop LCD32F4BV1 driver system when in pseudo stop mode.
1 LCD operates normally in pseudo stop mode.
10.3.2.3 LCD Frontplane Enable Register 0–3 (FPENR0–FPENR3)
Module Base + 0x0002
7
R
FP7EN
W
Reset
0
6
5
4
3
2
1
FP6EN
FP5EN
FP4EN
FP3EN
FP2EN
FP1EN
0
0
0
0
0
0
Figure 10-4. LCD Frontplane Enable Register 0 (FPENR0)
Module Base + 0x0003
7
R
FP15EN
W
Reset
0
6
5
4
3
2
FP14EN
FP13EN
FP12EN
FP11EN
FP10EN
0
0
0
0
0
Figure 10-5. LCD Frontplane Enable Register 1 (FPENR1)
1
FP9EN
0
0
FP0EN
0
0
FP8EN
0
MC9S12XHZ512 Data Sheet, Rev. 1.06
416
Freescale Semiconductor