S912XHZ512F1VAG Datasheet, PDF (109/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 2 Port Integration Module (S12XHZPIMV1)
Table 2-44. DDRT Field Descriptions
Field
7:0
Data Direction Port T
DDRT[7:0] 0 Associated pin is configured as input.
1 Associated pin is configured as output.
Description
2.3.11.4 Port T Reduced Drive Register (RDRT)
Module Base + 0x0003
7
R
RDRT7
W
6
RDRT6
5
RDRT5
4
RDRT4
3
RDRT3
2
RDRT2
1
RDRT1
0
RDRT0
Reset
0
0
0
0
0
0
0
0
Figure 2-61. Port T Reduced Drive Register (RDRT)
Read: Anytime. Write: Anytime.
This register configures the drive strength of configured output pins as either full or reduced. If a pin is
configured as input, the corresponding Reduced Drive Register bit has no effect.
Table 2-45. RDRT Field Descriptions
Field
Description
7:0
Reduced Drive Port T
RDRT[7:0] 0 Full drive strength at output.
1 Associated pin drives at about 1/3 of the full drive strength.
MC9S12XHZ512 Data Sheet, Rev. 1.06
Freescale Semiconductor
109