S912XHZ512F1VAG Datasheet, PDF (959/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Appendix E Detailed Register Map
Detailed MSCAN Foreground Receive and Transmit Buffer Layout (continued)
Address Name
0xXXX4
–
0xXXXB
CANxRDSR0–
CANxRDSR7
R
W
R
0xXXXC CANRxDLR
W
R
0xXXXD Reserved
W
R
0xXXXE CANxRTSRH
W
R
0xXXXF CANxRTSRL
W
Extended ID R
CANxTIDR0 W
0xXX10
Standard ID R
W
Extended ID R
0xXX0x ^{CANxTIDR1 W}
XX10 Standard ID R
W
Extended ID R
CANxTIDR2 W
0xXX12
Standard ID R
W
Extended ID R
CANxTIDR3 W
0xXX13
Standard ID R
W
0xXX14
–
0xXX1B
CANxTDSR0– ^R
CANxTDSR7 ^W
R
0xXX1C CANxTDLR
W
R
0xXX1D CANxTTBPR
W
R
0xXX1E CANxTTSRH
W
R
0xXX1F CANxTTSRL
W
Bit 7
DB7
TSR15
TSR7
ID28
ID10
ID20
ID2
ID14
ID6
DB7
PRIO7
TSR15
TSR7
Bit 6
DB6
TSR14
TSR6
ID27
ID9
ID19
ID1
ID13
ID5
DB6
PRIO6
TSR14
TSR6
Bit 5
DB5
TSR13
TSR5
ID26
ID8
ID18
ID0
ID12
ID4
DB5
PRIO5
TSR13
TSR5
Bit 4
DB4
TSR12
TSR4
ID25
ID7
SRR=1
RTR
ID11
ID3
DB4
PRIO4
TSR12
TSR4
Bit 3
DB3
DLC3
TSR11
TSR3
ID24
ID6
IDE=1
IDE=0
ID10
ID2
DB3
DLC3
PRIO3
TSR11
TSR3
Bit 2
DB2
DLC2
TSR10
TSR2
ID23
ID5
ID17
ID9
ID1
DB2
DLC2
PRIO2
TSR10
TSR2
Bit 1
DB1
DLC1
TSR9
TSR1
ID22
ID4
ID16
ID8
ID0
DB1
DLC1
PRIO1
TSR9
TSR1
Bit 0
DB0
DLC0
TSR8
TSR0
ID21
ID3
ID15
ID7
RTR
DB0
DLC0
PRIO0
TSR8
TSR0
MC9S12XHZ512 Data Sheet, Rev. 1.06
Freescale Semiconductor
959