S912XHZ512F1VAG Datasheet, PDF (781/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 22 S12X Debug (S12XDBGV3) Module
22.3.2.8 Comparator Register Descriptions
Each comparator has a bank of registers that are visible through an 8-byte window in the S12XDBG
module register address map. Comparators A and C consist of 8 register bytes (3 address bus compare
registers, two data bus compare registers, two data bus mask registers and a control register).
Comparators B and D consist of four register bytes (three address bus compare registers and a control
register).
Each set of comparator registers is accessible in the same 8-byte window of the register address map and
can be accessed using the COMRV bits in the DBGC1 register. If the Comparators B or D are accessed
through the 8-byte window, then only the address and control bytes are visible, the 4 bytes associated with
data bus and data bus masking read as zero and cannot be written. Furthermore the control registers for
comparators B and D differ from those of comparators A and C.
0x0028
0x0029
0x002A
0x002B
0x002C
0x002D
0x002E
0x002F
Table 22-28. Comparator Register Layout
CONTROL
ADDRESS HIGH
ADDRESS MEDIUM
ADDRESS LOW
DATA HIGH COMPARATOR
DATA LOW COMPARATOR
DATA HIGH MASK
DATA LOW MASK
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Comparators A,B,C,D
Comparators A,B,C,D
Comparators A,B,C,D
Comparators A,B,C,D
Comparator A and C only
Comparator A and C only
Comparator A and C only
Comparator A and C only
22.3.2.8.1 Debug Comparator Control Register (DBGXCTL)
The contents of this register bits 7 and 6 differ depending upon which comparator registers are visible in
the 8-byte window of the DBG module register address map.
Address: 0x0028
7
R
0
W
6
5
4
3
2
1
NDB
TAG
BRK
RW
RWE
SRC
Reset
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 22-13. Debug Comparator Control Register (Comparators A and C)
0
COMPE
0
Address: 0x0028
7
6
5
4
3
2
1
R
SZE
SZ
TAG
BRK
RW
RWE
SRC
W
Reset
0
0
0
0
0
0
0
Figure 22-14. Debug Comparator Control Register (Comparators B and D)
Read: Anytime. See Table 22-29 for visible register encoding.
0
COMPE
0
MC9S12XHZ512 Data Sheet Rev. 1.06
Freescale Semiconductor
781