S912XHZ512F1VAG Datasheet, PDF(52/978 Page) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

S912XHZ512F1VAG Datasheet, PDF (52/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

◁

Chapter 1 MC9S12XHZ Family Device Overview

Table 1-9. Interrupt Vector Locations (Sheet 1 of 3)

Vector Address1

XGATE

Channel ID2

0xFFFE

0xFFFC

0xFFFA

Vector base + 0xF8

Vector base+ 0xF6

Vector base+ 0xF4

Vector base+ 0xF2

Vector base+ 0xF0

Vector base+ 0xEE

Vector base + 0xEC

Vector base+ 0xEA

Vector base+ 0xE8

Vector base+ 0xE6

Vector base+ 0xE4

Vector base + 0xE2

Vector base+ 0xE0

Vector base+ 0xDE

Vector base+ 0xDC

Vector base + 0xDA

Vector base + 0xD8

Vector base+ 0xD6

â

â

â

â

â

â

â

0x78

0x77

0x76

0x75

0x74

0x73

0x72

0x71

0x70

0x6F

0x6E

0x6D

0x6C

0x6B

Vector base + 0xD4

0x6A

Vector base + 0xD2

Vector base + 0xD0

Vector base + 0xCE

Vector base + 0xCC

Vector base + 0xCA

Vector base + 0xC8

Vector base + 0xC6

Vector base + 0xC4

Vector base + 0xC2

Vector base + 0xC0

Vector base + 0xBE

0x69

0x68

0x67

0x66

0x65

0x64

0x63

0x62

0x61

0x60

0x5F

Interrupt Source

System reset or illegal access reset

Clock monitor reset

COP watchdog reset

Unimplemented instruction trap

SWI

XIRQ

IRQ

Real time interrupt

Enhanced capture timer channel 0

Enhanced capture timer channel 1

Enhanced capture timer channel 2

Enhanced capture timer channel 3

Enhanced capture timer channel 4

Enhanced capture timer channel 5

Enhanced capture timer channel 6

Enhanced capture timer channel 7

Enhanced capture timer overï¬ow

Pulse accumulator A overï¬ow

Pulse accumulator input edge

SPI

SCI0

SCI1

ATD

Reserved

Port AD

Reserved

Modulus down counter underï¬ow

Pulse accumulator B overï¬ow

CRG PLL lock

CRG self-clock mode

Reserved

IIC0 bus

Reserved

CCR

Mask

None

None

None

None

None

X Bit

I bit

I bit

I bit

I bit

I bit

I bit

I bit

I bit

I bit

I bit

I bit

I bit

I bit

I bit

I bit

I bit

I bit

I bit

I bit

I bit

I bit

I bit

I bit

I bit

I bit

I bit

I bit

Local Enable

None

PLLCTL (CME, SCME)

COP rate select

None

None

None

IRQCR (IRQEN)

CRGINT (RTIE)

TIE (C0I)

TIE (C1I)

TIE (C2I)

TIE (C3I)

TIE (C4I)

TIE (C5I)

TIE (C6I)

TIE (C7I)

TSRC2 (TOF)

PACTL (PAOVI)

PACTL (PAI)

SPCR1 (SPIE, SPTIE)

SCI0CR2

(TIE, TCIE, RIE, ILIE)

SCI1CR2

(TIE, TCIE, RIE, ILIE)

ATDCTL2 (ASCIE)

Reserved

PIEAD (PIEAD7 - PIEAD0)

Reserved

MCCTL(MCZI)

PBCTL(PBOVI)

CRGINT(LOCKIE)

CRGINT (SCMIE)

Reserved

IB0CR (IBIE)

Reserved

MC9S12XHZ512 Data Sheet, Rev. 1.06

52

Freescale Semiconductor

▷