S912XHZ512F1VAG Datasheet, PDF (625/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 17
Periodic Interrupt Timer (S12PIT24B4CV1)
17.1 Introduction
The period interrupt timer (PIT) is an array of 24-bit timers that can be used to trigger peripheral modules
or raise periodic interrupts. Refer to Figure 17-1 for a simplified block diagram.
17.1.1 Glossary
PIT
ISR
CCR
SoC
micro time bases
Acronyms and Abbreviations
Periodic Interrupt Timer
Interrupt Service Routine
Condition Code Register
System on Chip
clock periods of the 16-bit timer modulus down-counters, which are generated by the 8-bit
modulus down-counters.
17.1.2 Features
The PIT includes these features:
• Four timers implemented as modulus down-counters with independent time-out periods.
• Time-out periods selectable between 1 and 2²⁴ bus clock cycles. Time-out equals m*n bus clock
cycles with 1 <= m <= 256 and 1 <= n <= 65536.
• Timers that can be enabled individually.
• Four time-out interrupts.
• Four time-out trigger output signals available to trigger peripheral modules.
• Start of timer channels can be aligned to each other.
17.1.3 Modes of Operation
Refer to the SoC guide for a detailed explanation of the chip modes.
• Run mode
This is the basic mode of operation.
• Wait mode
MC9S12XHZ512 Data Sheet, Rev. 1.06
Freescale Semiconductor
625