S912XHZ512F1VAG Datasheet, PDF (580/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 15 Serial Communication Interface (S12SCIV5)
1 _{The address bit identifies the frame as an address}
character. See Section 15.4.6.6, “Receiver Wakeup”.
15.4.4 Baud Rate Generation
A 13-bit modulus counter in the baud rate generator derives the baud rate for both the receiver and the
transmitter. The value from 0 to 8191 written to the SBR12:SBR0 bits determines the bus clock divisor.
The SBR bits are in the SCI baud rate registers (SCIBDH and SCIBDL). The baud rate clock is
synchronized with the bus clock and drives the receiver. The baud rate clock divided by 16 drives the
transmitter. The receiver has an acquisition rate of 16 samples per bit time.
Baud rate generation is subject to one source of error:
• Integer division of the bus clock may not give the exact target frequency.
Table 15-16 lists some examples of achieving target baud rates with a bus clock frequency of 25 MHz.
When IREN = 0 then,
SCI baud rate = SCI bus clock / (16 * SCIBR[12:0])
Table 15-16. Baud Rates (Example: Bus Clock = 25 MHz)
Bits
SBR[12:0]
41
81
163
326
651
1302
2604
5208
Receiver
Clock (Hz)
609,756.1
308,642.0
153,374.2
76,687.1
38,402.5
19,201.2
9600.6
4800.0
Transmitter
Clock (Hz)
38,109.8
19,290.1
9585.9
4792.9
2400.2
1200.1
600.0
300.0
Target
Baud Rate
38,400
19,200
9,600
4,800
2,400
1,200
600
300
Error
(%)
.76
.47
.16
.15
.01
.01
.00
.00
MC9S12XHZ512 Data Sheet, Rev. 1.06
580
Freescale Semiconductor