S912XHZ512F1VAG Datasheet, PDF (127/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 2 Port Integration Module (S12XHZPIMV1)
2.4.4 Reduced Drive Register
If the port is used as an output the Reduced Drive Register allows the configuration of the drive strength.
2.4.5 Pull Device Enable Register
The Pull Device Enable Register turns on a pull-up or pull-down device. The pull device becomes active
only if the pin is used as an input or as a wired-or output.
2.4.6 Polarity Select Register
The Polarity Select Register selects either a pull-up or pull-down device if enabled. The pull device
becomes active only if the pin is used as an input or as a wired-or output.
2.4.7 Pin Configuration Summary
The following table summarizes the effect of various configuration in the Data Direction (DDR),
Input/Output (I/O), reduced drive (RDR), Pull Enable (PE), Pull Select (PS) and Interrupt Enable (IE)
register bits. The PS configuration bit is used for two purposes:
1. Configure the sensitive interrupt edge (rising or falling), if interrupt is enabled.
2. Select either a pull-up or pull-down device if PE is set to “1”.
Table 2-66. Pin Configuration Summary
DDR
IO
RDR
PE
PS
IE¹
Function²
Pull Device
Interrupt
0
X
X
0
X
0
Input
Disabled
Disabled
0
X
X
1
0
0
Input
Pull Up
Disabled
0
X
X
1
1
0
Input
Pull Down
Disabled
0
X
X
0
0
1
Input
Disabled
Falling Edge
0
X
X
0
1
1
Input
Disabled
Rising Edge
0
X
X
1
0
1
Input
Pull Up
Falling Edge
0
X
X
1
1
1
Input
Pull Down
Rising Edge
1
0
0
X
X
0
Output to 0, Full Drive
Disabled
Disabled
1
1
0
X
X
0
Output to 1, Full Drive
Disabled
Disabled
1
0
1
X
X
0
Output to 0, Reduced Drive
Disabled
Disabled
1
1
1
X
X
0
Output to 1, Reduced Drive
Disabled
Disabled
1
0
0
X
0
1
Output to 0, Full Drive
Disabled
Falling Edge
1
1
0
X
1
1
Output to 1, Full Drive
Disabled
Rising Edge
1
0
1
X
0
1
Output to 0, Reduced Drive
Disabled
Falling Edge
1
1
1
X
1
1
Output to 1, Reduced Drive
Disabled
Rising Edge
1 _{Applicable only on Port AD.}
2 _{Digital outputs are disabled and digital input logic is forced to “1” when an analog module associated with the port is enabled.}
MC9S12XHZ512 Data Sheet, Rev. 1.06
Freescale Semiconductor
127