S912XHZ512F1VAG Datasheet, PDF (681/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
Table 19-4. OC7M Field Descriptions
Field
Description
7:0
OC7M[7:0]
Output Compare Mask Action for Channel 7:0
A channel 7 event, which can be a counter overflow when TTOV[7] is set or a successful output compare
on channel 7, overrides any channel 6:0 compares. For each OC7M bit that is set,the output compare
action reflects the corresponding OC7D bit.
0 The corresponding OC7Dx bit in the output compare 7 data register will not be transferred to the timer port on
a channel 7 event, even if the corresponding pin is setup for output compare.
1 The corresponding OC7Dx bit in the output compare 7 data register will be transferred to the timer port on a
channel 7 event.
Note: The corresponding channel must also be setup for output compare (IOSx = 1 andOCPDx = 0) for data to
be transferred from the output compare 7 data register to the timer port.
19.3.2.4 Output Compare 7 Data Register (OC7D)
Module Base + 0x0003
R
W
Reset
7
OC7D7
0
6
OC7D6
5
OC7D5
4
OC7D4
3
OC7D3
2
OC7D2
0
0
0
0
0
Figure 19-6. Output Compare 7 Data Register (OC7D)
Read or write: Anytime
All bits reset to zero.
1
OC7D1
0
0
OC7D0
0
Table 19-5. OC7D Field Descriptions
Field
Description
7:0
Output Compare 7 Data Bits — A channel 7 event, which can be a counter overflow when TTOV[7] is set or A
OC7D[7:0] channel 7 output compare can cause bits in the output compare 7 data register to transfer to the timer port data
register depending on the output compare 7 mask register.
19.3.2.5 Timer Count Register (TCNT)
Module Base + 0x0004
R
W
Reset
15
TCNT15
0
14
TCNT14
13
TCNT13
12
TCNT12
11
TCNT11
10
TCNT10
0
0
0
0
0
Figure 19-7. Timer Count Register High (TCNT)
9
TCNT9
0
8
TCNT8
0
MC9S12XHZ512 Data Sheet Rev. 1.06
Freescale Semiconductor
681