S912XHZ512F1VAG Datasheet, PDF (121/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3.14 Port W
Port W is associated with the stepper stall detect (SSD5 and SSD4) and motor controller (MC5 and MC4)
modules. Each pin is assigned to these modules according to the following priority: SSD5/SSD4 >
MC5/MC4 > general-purpose I/O.
If SSD5 module is enabled, the PW[7:4] pins are controlled by the SSD5 module. If SSD5 module is
disabled, the PW[7:4] pins are controlled by the motor control PWM channels 11 and 10 (MC5).
If SSD4 module is enabled, the PW[3:0] pins are controlled by the SSD4 module. If SSD4 module is
disabled, the PW[3:0] pins are controlled by the motor control PWM channels 9 and 8 (MC4).
Refer to the SSD and MC block description chapters for information on enabling and disabling the SSD
module and the motor control PWM channels respectively.
During reset, port W pins are configured as high-impedance inputs.
2.3.14.1 Port W I/O Register (PTW)
Module Base + 0x0040
R
W
MC:
SSD5/
SSD4
Reset
7
PTW7
M5C1P
M5SINP
0
6
PTW6
5
PTW5
4
PTW4
3
PTW3
2
PTW2
1
PTW1
0
PTW0
M3C1M
M5C0P
M5C0M
M4C1P
M4C1M
M3SINM M5COSP M5COSM M4SINP
M4SINM
0
0
0
0
0
Figure 2-78. Port W I/O Register (PTW)
M4C0P
M4COSP
0
M4C0M
M4COSM
0
Read: Anytime. Write: anytime.
If the associated data direction bit (DDRWx) is set to 1 (output), a read returns the value of the I/O register
bit.
If the associated data direction bit (DDRWx) is set to 0 (input) and the slew rate is enabled, the associated
I/O register bit (PTWx) reads “1”.
If the associated data direction bit (DDRWx) is set to 0 (input) and the slew rate is disabled, a read returns
the value of the pin.
MC9S12XHZ512 Data Sheet, Rev. 1.06
Freescale Semiconductor
121