S912XHZ512F1VAG Datasheet, PDF (59/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 2 Port Integration Module (S12XHZPIMV1)
2.2 External Signal Description
This section lists and describes the signals that connect off chip.
Table 2-1 shows all the pins and their functions that are controlled by the S12XHZPIM. The order in which
the pin functions are listed represents the functions priority (top – highest priority, bottom – lowest
priority).
Table 2-1. Detailed Signal Descriptions (Sheet 1 of 6)
Port
—
A
B
C
D
Pin Name
Pin Function
and Priority
BKGD
PA[7:0]
PB[7:1]
PB[0]
PC[7:0]
MODC
BKGD
ADDR[15:8]
mux IVD[15:8]
FP[15:8]
GPIO
ADDR[7:1]
mux IVD[7:1]
FP[7:1]
GPIO
ADDR0
mux IVD0
UDS
FP[0]
GPIO
DATA[15:8]
GPIO
PD[7:0] DATA[7:0]
GPIO
I/O
Description
I MODC input during RESET
I/O S12X_BDM communication pin
O High-order external bus address output
(multiplexed with IVIS data)
O LCD frontplane driver
I/O General-purpose I/O
O Low-order external bus address output
(multiplexed with IVIS data)
O LCD frontplane driver
I/O General-purpose I/O
O Low-order external bus address output
(multiplexed with IVIS data)
O Upper data strobe
O LCD frontplane driver
I/O General-purpose I/O
I/O High-order bidirectional data input/output
Configurable for reduced input threshold
I/O General-purpose I/O
I/O Low-order bidirectional data input/output
Configurable for reduced input threshold
I/O General-purpose I/O
Pin Function
after Reset
BKGD
Mode dependent
Mode dependent
Mode dependent
Mode dependent
MC9S12XHZ512 Data Sheet, Rev. 1.06
Freescale Semiconductor
59