S912XHZ512F1VAG Datasheet, PDF (43/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 1 MC9S12XHZ Family Device Overview
1.2.3.38 PS7 / SS — Port S I/O Pin 7
PS7 is a general-purpose input or output pin. It can be configured as slave select pin SS of the serial
peripheral interface (SPI).
1.2.3.39 PS6 / SCK — Port S I/O Pin 6
PS6 is a general-purpose input or output pin. It can be configured as serial clock pin SCK of the serial
peripheral interface (SPI).
1.2.3.40 PS5 / MOSI — Port S I/O Pin 5
PS5 is a general-purpose input or output pin. It can be configured as the master output (during master
mode) or slave input (during slave mode) pin MOSI of the serial peripheral interface (SPI).
1.2.3.41 PS4 / MISO — Port S I/O Pin 4
PS4 is a general-purpose input or output pin. It can be configured as master input (during master mode) or
slave output (during slave mode) pin MISO for the serial peripheral interface (SPI).
1.2.3.42 PS3 / TXD1 — Port S I/O Pin 3
PS3 is a general-purpose input or output pin. It can be configured as transmit pin TXD1 of the serial
communication interface 1 (SCI1).
1.2.3.43 PS2 / RXD1 / CS2 — Port S I/O Pin 2
PS2 is a general-purpose input or output pin. It can be configured as receive pin RXD1 of the serial
communication interface 1 (SCI1). It can be configured to provide a chip-select output.
1.2.3.44 PS1 / TXD0 — Port S I/O Pin 1
PS1 is a general-purpose input or output pin. It can be configured as transmit pin TXD0 of the serial
communication interface 0 (SCI0).
1.2.3.45 PS0 / RXD0 — Port S I/O Pin 0
PS0 is a general-purpose input or output pin. It can be configured as receive pin RXD0 of the serial
communication interface 0 (SCI0).
MC9S12XHZ512 Data Sheet, Rev. 1.06
Freescale Semiconductor
43