S912XHZ512F1VAG Datasheet, PDF (407/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 9 Analog-to-Digital Converter (ATD10B16CV4) Block Description
Entering wait mode, the ATD conversion either continues or halts for low power depending on the
logical value of the AWAIT bit.
• Freeze Mode
Writing ADPU = 0 (Note that all ATD registers remain accessible.): This aborts any A/D
conversion in progress.
In freeze mode, the ATD10B16C will behave according to the logical values of the FRZ1 and FRZ0
bits. This is useful for debugging and emulation.
NOTE
The reset value for the ADPU bit is zero. Therefore, when this module is
reset, it is reset into the power down state.
9.5 Initialization/Application Information
9.5.1 Setting up and starting an A/D conversion
The following describes a typical setup procedure for starting A/D conversions. It is highly recommended
to follow this procedure to avoid common mistakes.
Each step of the procedure will have a general remark and a typical example
9.5.1.1 Step 1
Power up the ATD and concurrently define other settings in ATDCTL2
Example: Write to ATDCTL2: ADPU=1 -> powers up the ATD, ASCIE=1 enable interrupt on finish of a
conversion sequence.
9.5.1.2 Step 2
Wait for the ATD Recovery Time t_REC before you proceed with Step 3.
Example: Use the CPU in a branch loop to wait for a defined number of bus clocks.
9.5.1.3 Step 3
Configure how many conversions you want to perform in one sequence and define other settings in
ATDCTL3.
Example: Write S4C=1 to do 4 conversions per sequence.
9.5.1.4 Step 4
Configure resolution, sampling time and ATD clock speed in ATDCTL4.
Example: Use default for resolution and sampling time by leaving SRES8, SMP1 and SMP0 clear. For a
bus clock of 40MHz write 9 to PR4-0, this gives an ATD clock of 0.5*40MHz/(9+1) = 2MHz which is
within the allowed range for f_ATDCLK.
MC9S12XHZ512 Data Sheet, Rev. 1.06
Freescale Semiconductor
407