S912XHZ512F1VAG Datasheet, PDF (606/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 16 Serial Peripheral Interface (S12SPIV4)
Table 16-4. Bidirectional Pin Configurations
Pin Mode
Normal
Bidirectional
Normal
Bidirectional
SPC0
0
1
0
1
BIDIROE
MISO
Master Mode of Operation
X
Master In
0
MISO not used by SPI
1
Slave Mode of Operation
X
Slave Out
0
Slave In
1
Slave I/O
MOSI
Master Out
Master In
Master I/O
Slave In
MOSI not used by SPI
16.3.2.3 SPI Baud Rate Register (SPIBR)
Module Base +0x0002
7
6
5
4
3
R
0
0
SPPR2
SPPR1
SPPR0
W
Reset
0
0
0
0
0
= Unimplemented or Reserved
2
SPR2
0
Figure 16-5. SPI Baud Rate Register (SPIBR)
Read: Anytime
Write: Anytime; writes to the reserved bits have no effect
Table 16-5. SPIBR Field Descriptions
1
SPR1
0
0
SPR0
0
Field
Description
6–4
SPI Baud Rate Preselection Bits — These bits specify the SPI baud rates as shown in Table 16-6. In master
SPPR[2:0] mode, a change of these bits will abort a transmission in progress and force the SPI system into idle state.
2–0
SPI Baud Rate Selection Bits — These bits specify the SPI baud rates as shown in Table 16-6. In master mode,
SPR[2:0] a change of these bits will abort a transmission in progress and force the SPI system into idle state.
The baud rate divisor equation is as follows:
BaudRateDivisor = (SPPR + 1) • 2^{(SPR + 1)}
The baud rate can be calculated with the following equation:
Baud Rate = BusClock / BaudRateDivisor
NOTE
For maximum allowed baud rates, please refer to the SPI Electrical
Specification in the Electricals chapter of this data sheet.
Eqn. 16-1
Eqn. 16-2
MC9S12XHZ512 Data Sheet, Rev. 1.06
606
Freescale Semiconductor