S912XHZ512F1VAG Datasheet, PDF (188/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 4 4 Kbyte EEPROM Module (S12XEETX4KV2)
then ECLKDIV register bits PRDIV8 and EDIV[5:0] are to be set as described in Figure 4-17.
For example, if the oscillator clock frequency is 950 kHz and the bus clock frequency is 10 MHz,
ECLKDIV bits EDIV[5:0] should be set to 0x04 (000100) and bit PRDIV8 set to 0. The resulting EECLK
frequency is then 190 kHz. As a result, the EEPROM program and erase algorithm timings are increased
over the optimum target by:
(200 – 190) ⁄ 200 × 100 = 5%
If the oscillator clock frequency is 16 MHz and the bus clock frequency is 40 MHz, ECLKDIV bits
EDIV[5:0] should be set to 0x0A (001010) and bit PRDIV8 set to 1. The resulting EECLK frequency is
then 182 kHz. In this case, the EEPROM program and erase algorithm timings are increased over the
optimum target by:
(200 – 182) ⁄ 200 × 100 = 9%
CAUTION
Program and erase command execution time will increase proportionally
with the period of EECLK. Because of the impact of clock synchronization
on the accuracy of the functional timings, programming or erasing the
EEPROM memory cannot be performed if the bus clock runs at less than 1
MHz. Programming or erasing the EEPROM memory with EECLK < 150
kHz should be avoided. Setting ECLKDIV to a value such that EECLK <
150 kHz can destroy the EEPROM memory due to overstress. Setting
ECLKDIV to a value such that (1/EECLK+Tbus) < 5 µs can result in
incomplete programming or erasure of the EEPROM memory cells.
If the ECLKDIV register is written, the EDIVLD bit is set automatically. If the EDIVLD bit is 0, the
ECLKDIV register has not been written since the last reset. If the ECLKDIV register has not been written
to, the EEPROM command loaded during a command write sequence will not execute and the ACCERR
flag in the ESTAT register will set.
MC9S12XHZ512 Data Sheet, Rev. 1.06
188
Freescale Semiconductor