S912XHZ512F1VAG Datasheet, PDF (455/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 11 Motor Controller (MC10B12CV2) Block Description
The motor controller channel frequency of operation can be calculated using the following formula if
DITH = 1:
Motor Channel Frequency (Hz) = _M------_C-----_P---_E--^f--_R^T---^C--_â‹---_M-------_⁄---₂-
NOTE
Both equations are only valid if MCPER is not equal to 0. M = 1 for left or
right aligned mode, M = 2 for center aligned mode.
Table 11-14 shows examples of the motor controller channel frequencies that can be generated based on
different peripheral bus clock frequencies and the prescaler value.
Table 11-14. Motor Controller Channel Frequencies (Hz),
MCPER = 256, DITH = 0, MCAM = 10, 01
Prescaler
1
1/2
1/4
1/8
16 MHz
62500
31250
15625
7813
Peripheral Bus Clock Frequency
10 MHz
39063
19531
9766
4883
8 MHz
31250
15625
7813
3906
5 MHz
19531
9766
4883
2441
4 MHz
15625
7813
3906
1953
NOTE
Due to the selectable slew rate control of the outputs, clipping may occur on
short output pulses.
11.4.4 Output Switching Delay
In order to prevent large peak current draw from the motor power supply, selectable delays can be used to
stagger the high logic level to low logic level transitions on the motor controller outputs. The timing delay,
t_d, is determined by the CD[1:0] bits in the corresponding channel control register (MCMCx) and is
selectable between 0, 1, 2, or 3 motor controller timer counter clock cycles.
NOTE
A PWM channel gets disabled at the next timer counter overflow without
notice of the switching delay.
MC9S12XHZ512 Data Sheet, Rev. 1.06
Freescale Semiconductor
455