S912XHZ512F1VAG Datasheet, PDF (180/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 4 4 Kbyte EEPROM Module (S12XEETX4KV2)
4.3.2.1 EEPROM Clock Divider Register (ECLKDIV)
The ECLKDIV register is used to control timed events in program and erase algorithms.
Module Base + 0x0000
R
W
Reset
7
EDIVLD
0
6
PRDIV8
5
EDIV5
4
EDIV4
3
EDIV3
2
EDIV2
0
0
0
0
0
= Unimplemented or Reserved
Figure 4-4. EEPROM Clock Divider Register (ECLKDIV)
1
EDIV1
0
0
EDIV0
0
All bits in the ECLKDIV register are readable, bits 6–0 are write once and bit 7 is not writable.
Table 4-2. ECLKDIV Field Descriptions
Field
Description
7
EDIVLD
6
PRDIV8
5:0
EDIV[5:0]
Clock Divider Loaded
0 Register has not been written.
1 Register has been written to since the last reset.
Enable Prescalar by 8
0 The oscillator clock is directly fed into the ECLKDIV divider.
1 Enables a Prescalar by 8, to divide the oscillator clock before feeding into the clock divider.
Clock Divider Bits — The combination of PRDIV8 and EDIV[5:0] effectively divides the EEPROM module input
oscillator clock down to a frequency of 150 kHz – 200 kHz. The maximum divide ratio is 512. Please refer to
Section 4.4.1.1, “Writing the ECLKDIV Register” for more information.
4.3.2.2 RESERVED1
This register is reserved for factory testing and is not accessible.
Module Base + 0x0001
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 4-5. RESERVED1
All bits read 0 and are not writable.
4.3.2.3 RESERVED2
This register is reserved for factory testing and is not accessible.
MC9S12XHZ512 Data Sheet, Rev. 1.06
180
Freescale Semiconductor