S912XHZ512F1VAG Datasheet, PDF (123/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

2.3.14.4 Port W Slew Rate Register (SRRW)
Chapter 2 Port Integration Module (S12XHZPIMV1)
Module Base + 0x0043
R
W
Reset
7
SRRW7
0
6
SRRW6
5
SRRW5
4
SRRW4
3
SRRW3
2
SRRW2
0
0
0
0
0
Figure 2-81. Port W Slew Rate Register (SRRW)
1
SRRW1
0
0
SRRW0
0
Read: anytime. Write: Anytime.
This register enables the slew rate control and disables the digital input buffer for port pins PW[7:0].
Table 2-62. SRRW Field Descriptions
Field
Description
7:0
Slew Rate Port W
SRRW[7:0] 0 Disables slew rate control and enables digital input buffer.
1 Enables slew rate control and disables digital input buffer.
2.3.14.5 Port W Pull Device Enable Register (PERW)
Module Base + 0x0044
7
R
PERW7
W
6
PERW6
5
PERW5
4
PERW4
3
PERW3
2
PERW2
1
PERW1
0
PERW0
Reset
0
0
0
0
0
0
0
0
Figure 2-82. Port W Pull Device Enable Register (PERW)
Read: Anytime. Write: Anytime.
This register configures whether a pull-up or a pull-down device is activated on configured input pins. If
a pin is configured as output, the corresponding Pull Device Enable Register bit has no effect.
Table 2-63. PERW Field Descriptions
Field
7:0
Pull Device Enable Port W
PERW[7:0] 0 Pull-up or pull-down device is disabled.
1 Pull-up or pull-down device is enabled.
Description
MC9S12XHZ512 Data Sheet, Rev. 1.06
Freescale Semiconductor
123