S912XHZ512F1VAG Datasheet, PDF (335/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 7 Clocks and Reset Generator (S12CRGV6)
7.3.1 Module Memory Map
Table 7-1 gives an overview on all CRG registers.
Table 7-1. CRG Memory Map
Address
Offset
Use
0x_00
CRG Synthesizer Register (SYNR)
0x_01
0x_02
CRG Reference Divider Register (REFDV)
CRG Test Flags Register (CTFLG)¹
0x_03
CRG Flags Register (CRGFLG)
0x_04
CRG Interrupt Enable Register (CRGINT)
0x_05
CRG Clock Select Register (CLKSEL)
0x_06
CRG PLL Control Register (PLLCTL)
0x_07
CRG RTI Control Register (RTICTL)
0x_08
0x_09
0x_0A
CRG COP Control Register (COPCTL)
CRG Force and Bypass Test Register (FORBYP)²
CRG Test Control Register (CTCTL)³
0x_0B
CRG COP Arm/Timer Reset (ARMCOP)
1 _{CTFLG is intended for factory test purposes only.}
2 _{FORBYP is intended for factory test purposes only.}
3 _{CTCTL is intended for factory test purposes only.}
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
NOTE
Register Address = Base Address + Address Offset, where the Base Address
is defined at the MCU level and the Address Offset is defined at the module
level.
MC9S12XHZ512 Data Sheet, Rev. 1.06
Freescale Semiconductor
335