S912XHZ512F1VAG Datasheet, PDF (100/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3.9.7 Port P Wired-OR Mode Register (WOMP)
Module Base + 0x001E
7
6
5
4
3
2
1
0
R
0
0
WOMP7
WOMP6
WOMP5
WOMP4
WOMP2
WOMPO
W
Reset
0
0
0
0
0
0
0
0
= Reserved or Unimplemented
Figure 2-48. Port P Wired-OR Mode Register (WOMP)
Read: Anytime. Write: Anytime.
This register selects whether a port P output is configured as push-pull or wired-or. When a Wired-OR
Mode Register bit is set to 1, the corresponding output pin is driven active low only (open drain) and a
high level is not driven. A Wired-OR Mode Register bit has no effect if the corresponding pin is configured
as an input.
If IIC is enabled and the corresponding PWM channels are disabled, the pins are configured as wired-or
and the corresponding Wired-OR Mode Register bits have no effect.
Table 2-36. WOMP Field Descriptions
Field
Description
7:4
Wired-OR Mode Port P
WOMP[7:4] 0 Output buffers operate as push-pull outputs.
1 Output buffers operate as open-drain outputs.
2
WOMP2
Wired-OR Mode Port P
0 Output buffers operate as push-pull outputs.
1 Output buffers operate as open-drain outputs.
0
WOMP0
Wired-OR Mode Port P
0 Output buffers operate as push-pull outputs.
1 Output buffers operate as open-drain outputs.
MC9S12XHZ512 Data Sheet, Rev. 1.06
100
Freescale Semiconductor