S912XHZ512F1VAG Datasheet, PDF (680/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
19.3.2.2 Timer Compare Force Register (CFORC)
Module Base + 0x0001
R
W
Reset
7
0
FOC7
0
6
0
FOC6
0
5
0
FOC5
0
4
0
FOC4
0
3
0
FOC3
0
2
0
FOC2
0
Figure 19-4. Timer Compare Force Register (CFORC)
Read or write: Anytime but reads will always return 0x0000 (1 state is transient).
All bits reset to zero.
1
0
FOC1
0
0
0
FOC0
0
Table 19-3. CFORC Field Descriptions
Field
Description
7:0
FOC[7:0]
Force Output Compare Action for Channel 7:0 — A write to this register with the corresponding data bit(s) set
causes the action which is programmed for output compare “x” to occur immediately. The action taken is the
same as if a successful comparison had just taken place with the TCx register except the interrupt flag does not
get set.
Note: A channel 7 event, which can be a counter overflow when TTOV[7] is set or A successful channel 7 output
compare overrides any channel 6:0 compares. If a forced output compare on any channel occurs at the
same time as the successful output compare, then the forced output compare action will take precedence
and the interrupt flag will not get set.
19.3.2.3 Output Compare 7 Mask Register (OC7M)
Module Base + 0x0002
R
W
Reset
7
OC7M7
0
6
OC7M6
0
5
OC7M5
0
4
OC7M4
0
3
OC7M3
0
2
OC7M2
0
Figure 19-5. Output Compare 7 Mask Register (OC7M)
Read or write: Anytime
All bits reset to zero.
1
OC7M1
0
0
OC7M0
0
MC9S12XHZ512 Data Sheet, Rev. 1.06
680
Freescale Semiconductor