S912XHZ512F1VAG Datasheet, PDF (768/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 22 S12X Debug (S12XDBGV3) Module
22.1.5 Block Diagram
TAGHITS
EXTERNAL TAGHI / TAGLO
XGATE S/W BREAKPOINT REQUEST
SECURE
CPU12X BUS
XGATE BUS
COMPARATOR A
COMPARATOR B
COMPARATOR C
COMPARATOR D
MATCH0
MATCH1
MATCH2
MATCH3
TAGS
BREAKPOINT REQUESTS
CPU12X & XGATE
TRIGGER
TAG &
TRIGGER
CONTROL
LOGIC
STATE
STATE
STATE SEQUENCER
TRACE
CONTROL
TRIGGER
READ TRACE DATA (DBG READ DATA BUS)
Figure 22-1. Debug Module Block Diagram
TRACE BUFFER
22.2 External Signal Description
The S12XDBG sub-module features two external tag input signals. See Device User Guide (DUG) for the
mapping of these signals to device pins. These tag pins may be used for the external tagging in emulation
modes only.
Pin Name
TAGHI
(See DUG)
TAGLO
(See DUG)
TAGLO
(See DUG)
Table 22-4. External System Pins Associated With S12XDBG
Pin Functions
TAGHI
TAGLO
Unconditional
Tagging Enable
Description
When instruction tagging is on, tags the high half of the instruction word being
read into the instruction queue.
When instruction tagging is on, tags the low half of the instruction word being
read into the instruction queue.
In emulation modes, a low assertion on this pin in the 7th or 8th cycle after the
end of reset enables the Unconditional Tagging function.
22.3 Memory Map and Registers
22.3.1 Module Memory Map
A summary of the registers associated with the S12XDBG sub-block is shown in Table 22-2. Detailed
descriptions of the registers and bits are given in the subsections that follow.
MC9S12XHZ512 Data Sheet, Rev. 1.06
768
Freescale Semiconductor